**Job Description**

Come join Intel's Client Engineering Group, responsible for designing Client SOCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptop and desktop computers.We are looking for an SoC (System on Chip) Physical Design Engineer, ready to research, design, develop, and test lead Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. This role is within Intel's highly-regarded Devices Development Group, headquartered in Portland, Oregon with additional sites in Penang, Malaysia, and Bangalore, India. Our bold purpose as a company is to 'create world-changing technology that enriches the lives of every person on earth' and this role is instrumental in furthering our mission to shape the future of technology.Your responsibilities may include but not be limited to:SoC, clock design, and power delivery integrationDriving performance optimization, including co-optimization work with process teams, to create best-in-class designs.Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.Static timing analysis constraint understanding and generation, clock stamping, and timing closure.Multiple Power Domain analysis using standard Power Formats UPF or CPFThe ideal candidate will exhibit behavioral traits that indicate:Self-motivator with strong problem solving skills.Excellent interpersonal skills, including written and verbal communication.Ability to work as part of a team and collaborate in a high-paced atmosphere.

**Qualifications**

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's degree with 5 years of experience, or master's degree with 3 years of experience, in Electrical Engineering, Computer Engineering, or any STEM related field.

3+ years of experience in backend design and/or integration in one of the following areas:

Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.

Static timing analysis constraint understanding and generation, clock stamping, and timing closure.

Multiple Power Domain analysis using standard Power Formats UPF or CPF

Preferred Qualifications:

7+ years of experience in backend design and/or integration

Product development and delivery on leading edge process nodes

**Inside this Business Group**

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

**Posting Statement**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Benefits**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, Colorado, New York, Washington, California: $123,419.00-$185,123.00

*Salary range dependent on a number of factors including location and experience

**Working Model**

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. **In certain circumstances the work model may change to accommodate business needs.**